500MS/s 4-b time interleaved SAR ADC using novel DAC architecture

The design and implementation details of a 4-bit time interleaved successive approximation register (SAR) analog to digital converter (ADC) for UWB application is presented in this paper. Major contribution of this paper is the proposal for a novel digital to analog converter (DAC) architecture which reduces the area required for capacitors by a factor of three, while the maximum error due mismatch between capacitors is reduced by 33% compared to the architecture reported in the literature. The ADC is implemented in .18 mum CMOS technology and has total power consumption of 17.6 mw at sampling frequency of 500 MS/s for an input swing of 1 V peak to peak. Proposed SAR ADC gives SNDR of 23.7 dB, SFDR of 31.5 dB and THD of -32.2 dB at Nyquist rate. The proposed ADC enables the input swing to be increased by 25% while maintaining figure of merit same compared to a SAR ADC reported in the literature.