By Topic

Multi network interface architectures for fault tolerant Network-on-Chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Rantala, V. ; Turku Centre for Comput. Sci. (TUCS), Turku, Finland ; Lehtonen, T. ; Liljeberg, P. ; Plosila, J.

The topology level fault tolerance of network-on-chip (NoC) can be improved with multi network interface (multi-NI) architectures. Multi-NI NoC architectures are based on connecting at least two network interfaces on each core. The aim is to improve fault tolerance on the architectural level which means the delivery of packets even when there are faulty links or routers in the network. This paper presents architectures and algorithms for multi-NI NoCs. The analysis of the proposed architectures and algorithms shows that some of them improve the fault tolerance of NoC with a reasonable overhead by decreasing the average hop counts and keeping the cores connectable even in the case of faults. With a multi-NI architecture the number of successfully delivered packets has been even doubled.

Published in:

Signals, Circuits and Systems, 2009. ISSCS 2009. International Symposium on

Date of Conference:

9-10 July 2009