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Self-termination scheme for high-speed chip-to-chip data communication

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2 Author(s)
P. Vijaya Sankara Rao ; Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur, India 721302 ; Pradip Mandal

In this work we propose self-termination scheme for high-speed current-mode differential signaling. This scheme eliminates the need of any dedicated passive terminator avoiding signal reflection both at the transmitter and receiver. We present fully differential, high speed transmitter/receiver(Tx/Rx) pair suitable for this self-terminated differential current-mode signaling scheme. We propose high-speed, power efficient self terminating transmitter with modified Cherry-Hooper topology. Also propose, self terminated, differential current-mode receiver realized by modified regulated gate cascode (RGC) based common-source (CS) trans-impedance amplifier (TIA) with folded active inductor peaking. The transmitter and receiver circuits are implemented in 1.8-V, 0.18-mum Digital CMOS technology with an fT of 27-GHz. The designed transmitter and receiver circuits, handle data rates up-to 8-Gb/s for the targeted BER of 10-12, while transmitting the data over backplane FR4 PCB trace of length 7.5-inch. The power consumed in the transmitter and receiver circuits is 10.31-mW and 10.17-mW respectively at 8-Gb/s data rate.

Published in:

Signals, Circuits and Systems, 2009. ISSCS 2009. International Symposium on

Date of Conference:

9-10 July 2009