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Decreasing error floor in LDPC codes by parity-check matrix extensions

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3 Author(s)
Sharon, E. ; Sch. of Electr. Eng., Tel Aviv Univ., Ramat Aviv, Israel ; Fainzilber, O. ; Litsyn, S.

High error floors in optimized irregular LDPC codes limit their usage in applications that require low error rates. We introduce new methods for lowering the error floor of LDPC codes, based on enhancing the code's parity-check matrix with additional linearly dependent and independent parity-checks. We prove NP hardness of certain optimization problems related to proposed methods and provide upper bound on the number of parity-checks that need to be added. We show that the proposed methods can lower the error floor of the code significantly, by several orders of magnitude, at negligible or no rate penalty.

Published in:

Information Theory, 2009. ISIT 2009. IEEE International Symposium on

Date of Conference:

June 28 2009-July 3 2009

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