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A sub-0.9V logic-compatible embedded DRAM with boosted 3T gain cell, regulated bit-line write scheme and PVT-tracking read reference bias

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4 Author(s)
Ki Chul Chun ; Dept. of ECE, University of Minnesota, 200 Union Street SE, Minneapolis, 55455, USA ; Pulkit Jain ; Jung Hwa Lee ; Chris H. Kim

Circuit techniques for enabling a sub-0.9V logic-compatible embedded DRAM (eDRAM) are presented. A boosted 3T gain cell increases read margin, enhances read speed and improves data retention time. A regulated bit-line write scheme and a read reference bias generator are proposed to cope with write disturbance issues and PVT variations. Measurement results from a 64kb eDRAM test chip implemented in a 65nm low-leakage CMOS process demonstrate the effectiveness of the proposed techniques.

Published in:

2009 Symposium on VLSI Circuits

Date of Conference:

16-18 June 2009