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A 5GHz phase-locked loop using dynamic phase-error compensation technique for fast settling in 0.18-µm CMOS

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3 Author(s)
Wei-Hao Chiu ; Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, 10617, R.O.C. ; Yu-Hsiang Huang ; Tsung-Hsien Lin

This paper presents a 5GHz phase-locked loop (PLL) with a fast-locking capability. During frequency locking, the proposed fast-settling technique dynamically adjusts the divide ratio of the frequency divider to keep the instantaneous phase error at the PFD input small. As a result, the locking time is greatly reduced. At a loop bandwidth of 20kHz, the measured settling time is less than 10µs, which is roughly 14× faster than a traditional PLL. Fabricated in a 0.18µm CMOS process, this PLL dissipates 9.5mA from a 1.8V supply. The measured phase noise is −117.5dBc/Hz at 1MHz offset.

Published in:

VLSI Circuits, 2009 Symposium on

Date of Conference:

16-18 June 2009

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