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A bandwidth tracking technique for a 65nm CMOS digital phase-locked loop

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3 Author(s)
Hsieh, P. ; University of California, Los Angeles, USA ; Maxey, J. ; Yang, C.-K.K.

This paper presents a technique to achieve the bandwidthtracking ability of digital PLLs used for clock generation in large digital systems. The technique uses replica delay cells in the DCO and the PD for ≫100× range of operating frequency. Measurement results show a near constant damping factor and the tracking of the loop bandwidth to reference frequency over 2× of core oscillation frequencies (2.5GHz–5.0GHz) and reference frequencies from 19.5MHz to 312MHz without calibration.

Published in:

VLSI Circuits, 2009 Symposium on

Date of Conference:

16-18 June 2009