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A 45nm 24MB on-die L3 cache for the 8-core multi-threaded Xeon® Processor

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12 Author(s)
Jonathan Chang ; Intel Corporation, 2200 Mission College Blvd. (SC12-408), Santa Clara, CA 95052, USA ; Szu-Liang Chen ; Wei Chen ; Siufu Chiu
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The 24-way set associative 24MB 8-ported L3 cache for the 8-core Xeon® Processor uses 0.3816 µm02 cell in a 45nm high-K dielectric metal gate technology 9-copper layers. It is protected by double-error correction/triple-error detection ECC. The basic building block is designed to support completely different floorplan styles on 2 processors with large L3 cache. Off die fuse storage enables high resolution repair coverage.

Published in:

2009 Symposium on VLSI Circuits

Date of Conference:

16-18 June 2009