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A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

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4 Author(s)
Chun-Cheng Liu ; Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan ; Soon-Jyh Chang ; Guan-Ying Huang ; Yin-Zu Lin

This paper reports a 10-bit 50MS/s SAR ADC with a set-and-down capacitor switching method. Compared to the conventional method, the average switching energy is reduced about 81%. At 50MS/s and 1.2V supply, the ADC consumes 0.92mW and achieves an SNDR of 52.78dB, resulting in an FOM of 52fJ/Conversion-step. Fabricated in a 0.13μm 1P8M CMOS technology, the ADC only occupies 0.075mm2 active area.

Published in:

VLSI Circuits, 2009 Symposium on

Date of Conference:

16-18 June 2009