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We describe the architecture of a FPGA-based self-calibrating Time to Digital Converter (TDC), specifically intended to measure the width of an input pulse. The configuration consists of two controllable ring oscillators with a very small difference in their frequencies, wherein this difference determines the achievable resolution. The calibration scheme relies on an accurate pulse-generator or external crystal-oscillator to provide a stable calibration pulse for the system. We implemented the TDC on an Altera Stratix II device where we measured a Least Significant Bit of 41 ps (an RMS resolution of 11.8 ps). We present details of the methods used to calibrate the TDC, the characterization process, and discuss the effects of variations in temperature and voltage.