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Use of a Contacted Buried {\rm n}^{+} Layer for Single Event Mitigation in 90 nm CMOS

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8 Author(s)
DasGupta, Sandeepan ; Electr. Eng. & Comput. Sci. Dept., Vanderbilt Univ., Nashville, TN, USA ; Amusan, O.A. ; Alles, M.L. ; Witulski, A.F.
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3-D TCAD simulation results predict reduction in single event charge collection, transient pulse widths, and charge sharing in a 90 nm bulk twin well process CMOS by using a contacted n+ buried layer.

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Nuclear Science, IEEE Transactions on  (Volume:56 ,  Issue: 4 )