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Notice of Violation of IEEE Publication Principles
Area efficient TAM controller and wrapper design for embedded cores

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2 Author(s)
G. Rohini ; St.Joseph's College of Enginering, Chennai, PO 600119, India ; S. Salivahanan

Notice of Violation of IEEE Publication Principles

"Area Efficient TAM Controller and Wrapper Design for Embedded Cores"
by G. Rohini and S. Salivahanan
in the 2009 International Conference on Control, Automation, Communication and Energy Conservation

After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles.

This paper copied substantial portions of text and figures from the papers cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper title) and without permission. The misconduct was committed specifically by G. Rohini (First author), and her actions were done without the knowledge or approval of S. Salivahanan (Second author).

Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following article:

"Developing Test Environment for Embedded Cores-Based System-on-a-Chip" (SOC)
By S. Das, D. Biswas, E.M. Petriu, M.H. Assaf and M. Sahinoglu
in the Instrumentation and Measurment Technology Conference - 2005

IEEE 1500 is a standard under development which intends to improve ease of test reuse and test integration with respect to the core-based SoCs. The subject paper proposes developing test environment and test methodologies for digital embedded cores based system-on-a-chip (SoC). The digital cores used in the study were constructed from ISCAS 85 combinational and ISCAS 89 sequential benchmark circuits. The wrapper that separates the core under test from other cores is assumed to be IEEE 1500-compliant. The test access mechanism plays an important role in transporting the test patterns to the desired core and the core responses to the output pin of the SoC. The faults were injected u- ing a fault simulator that generates tests for the core. The cores and test access mechanism were described using VHDL. The test access mechanism (TAM) provides the connection between the test sources, cores, and test sinks, and is crucial in any SoC design. The outcome was the fault coverage of all the cores being tested. Area overhead and power consumption are taken into account in our scheme. Some experiment results based on a sample SoC are reported, showing the effectiveness of the proposed approach in terms of area overhead.

Published in:

Control, Automation, Communication and Energy Conservation, 2009. INCACEC 2009. 2009 International Conference on

Date of Conference:

4-6 June 2009