Design of low power Asynchronous Pipelined Systems with Input Change Detection Circuit

In this paper, a novel technique, Input Change Detection (ICD) Circuit is proposed to reduce the dynamic power consumption of the Asynchronous Pipelined Systems with Bundled-Data Protocol. For every operand, a request pulse is given to the asynchronous pipelined system to process the operands, immaterial of whether the successive operands are same or different. This increases the dynamic power consumption of the system. Because, when the successive operands are same, the system need not be operated and the required result is obtained by holding the previous output. Based on this finding, the proposed ICD technique issues the request pulse only when the successive operands are different. If the successive operands are same, the system will not process the inputs but holds the previous output, hence reduces the dynamic power consumption. This technique is exploited in the 3times3 and 8times8 Braun array multipliers implemented on Altera Stratix II EP2S60F1020C4 FPGA and the results are compared with that of the asynchronous pipelined multipliers without ICD technique. For an input data stream with repeated operands, the dynamic power dissipation of the Braun array multipliers with the proposed technique is reduced approximately by 50% compared to that of the same without ICD. The area taken by the ICD circuit on 3x3 Braun array multiplier is 35% but on 8times8 Braun array multiplier, it is 10%. Hence the area of the ICD circuit is not linearly increasing with the complexity of the operation performed by the circuit. The technique proposed in this paper is also applicable for ASICs and FPGAs from other vendors.