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Rate-optimal static scheduling of DSP data flow graphs onto multiprocessors using circuit contraction

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3 Author(s)
Shatnawi, A. ; Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada ; Ahmad, M.O. ; Swamy, M.N.S.

This paper is concerned with the compile-time (static) scheduling of data flow graphs (DFGs) onto multiprocessor systems. It mainly concentrates on producing a rate-optimal time schedule that achieves the minimum iteration period, known as the iteration period bound. A combinatorial theory is developed to produce a rate-optimal time schedule for a fully specified DFG. The DFG is first converted to a critical graph by making all its circuits critical. Next, it is transformed into an acyclic graph through a sequence of circuit contractions. An algorithm is then proposed which achieves the time scheduling of the given DFG by first scheduling the acyclic graph, followed by a scheduling of the critical circuits in an order which is reverse to that of their contraction

Published in:

Circuits and Systems, 1995. ISCAS '95., 1995 IEEE International Symposium on  (Volume:2 )

Date of Conference:

30 Apr-3 May 1995