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Implementing and engineering signal processing applications so that they effectively exploit the characteristics of novel multi-core and even multiple multi-core platforms represents a big challenge. In particular, in many signal processing applications several algorithms are invoked in cascade and concur in generating quite a complex code from the algorithmic and computational viewpoint, like for instance CODECs, which in addition must also cope with real-time constraints. In a major effort to improve the performance of this class of applications on multi-core processors, we present a novel design methodology based on a thread-level parallelization and several algorithmic optimizations, which deploy of state-of-the-art algorithm engineering techniques to obtain an ldquooptimum job placementrdquo on novel multiple multi-core platforms in a structured and automatized way. We introduce also some degree of parametrization, which depends on the architectural characteristics of the chosen platform. This allows the design methodology to be more flexible and adaptable to evolving hardware features such as the increasing number and the characteristics of cores, memory and/or peripherals availability. Our approach is based on the automatization of the design flow by identifying in a first step ldquoparallel jobsrdquo, or ldquosmall threadsrdquo which, in a subsequent step, can be properly scheduled on the hardware resources available (cores), by taking into account also customized optimality criteria.