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An efficient stream memory architecture for heterogeneous multicore processor

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6 Author(s)
RangYu Deng ; Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China ; Weixia Xu ; Qiang Dou ; Hongwei Zhou
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It is challenging to design a high performance memory sub-system for heterogeneous multicore processor FT64-3, which features 18 on chip 64-bit float function units. In this paper, we propose a parallel stream memory architecture that can greatly leverage the design idea of exploiting memory level parallelism for higher memory throughput., Experimental results and analysis for kernel algorithms are presented in the paper to show the efficiency and rationale of our design. By employing our parallel stream memory architecture, the performance of FT64-3 with a is 2-3 orders better than FT64-2 when running at the same clock frequency of 500 MHz, and is comparable to Itanium2 running at 1.6 GHz but with less hardware cost.

Published in:

Computers and Communications, 2009. ISCC 2009. IEEE Symposium on

Date of Conference:

5-8 July 2009