By Topic

Implementation of a 64-point FFT on a Multi-Processor System-on-Chip

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Airoldi, R. ; Dept. of Comput. Syst., Tampere Univ. of Technol., Tampere, Finland ; Garzia, F. ; Nurmi, J.

This paper describes the implementation of a 64-point FFT on a Multi-Processor System-on-Chip (MPSoC) composed of 9 homogeneous clusters. Each cluster is built around a RISC processor. The implementation technique adopted for the mapping of the FFT produces a speed-up of 6× which is close to the theoretical limit. This is due to a reduced overhead of intra-clusters communication.

Published in:

Research in Microelectronics and Electronics, 2009. PRIME 2009. Ph.D.

Date of Conference:

12-17 July 2009