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Significant demand for utlra-low power applications has provided an advantage for circuits capable of sub-threshold operation. The reduction of the supply voltage (Vdd) below the threshold voltage (VT ) of transistors, or sub-threshold, provides minimum energy consumption in digital CMOS logic. The exponential dependence of the drain current on VT variations leads to increased overdesign if sub-threshold circuits are to be robust. One solution to variability robustness is timing error detection (TED). Presented here is a TED latch capable of subthreshold operation. It was designed in 65 nm CMOS, has an operating voltage range of 0.2 V through 1.2 V, and a minimum energy point (MEP) of 0.4 V. At the MEP, the average power consumption for one clock period and an activity factor of alpha=0.5 is 0.37 nW. The area of the TED latch is 93 mum2.