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Low frequency clock synchronization technique for low signal to noise ratio (SNR) signal recoery from noise environment

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3 Author(s)

This paper presents low frequency clock synchronization using digital frequency divider component in the lock-in amplifier. To extract the interesting low frequency DC signal which is under a few hundred kHz low SNR signal from the much stronger noise environment, exact input signal frequency information should be known. In the case of implementation this system, circuit designer will meet the problem to find or implement low frequency clock generator. In this paper, we propose to convert high frequency signal to low frequency clock using 1/n series flip flop divider for down conversion mixed filtering in lock-in amplifier. This simple but novel idea will solve the physical problem to implement lock-in amplifier for low frequency signal DC level detection application in the fields of bio-signal sensing or nano-ampere signal detection application.

Published in:

Digital Signal Processing, 2009 16th International Conference on

Date of Conference:

5-7 July 2009