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Spatial feature based reconfigurable H.264/AVC integer motion estimation architecture for HDTV video encoder

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3 Author(s)
Yiqing Huang ; Waseda University, 2-7, Hibikino, Wakamatsu, Kitakyushu, Fukuoka, Japan ; Qin Liu ; Takeshi Ikenaga

In this paper, we contribute one reconfigurable integer motion estimation (IME) architectures (namely RPPSAD) based on adaptive algorithm. Firstly, based on the pixel difference analysis, the spatial redundancy is further exploited and three subsampling patterns are selected adaptively for the IME process. Secondly, in order to achieve data reuse and power reduction in memory part, the reference pixels in search window are reorganization into two memory groups, which output pixel data interactively for adaptive subsampling. Moreover, a compressor tree based circuit level optimization is included in our design to reduce hardware cost. Synthesized with TSMC 0.18 um technology, averagely 10 k gates hardware can be reduced for the whole IME engine based on our optimization. With 481 k gates at 110.5 MHz, one 720-p, 30-fps HDTV integer motion estimation engine is designed. Compared with previous work, our design can achieve 39.8% reduction in power consumption with only 3.44% increase in hardware.

Published in:

2009 16th International Conference on Digital Signal Processing

Date of Conference:

5-7 July 2009