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Emerging DSP applications have different latency, energy consumption and quality of service (QoS) requirements. An implementation of such applications requires a large number of intellectual property (IP) cores, communicating with each other, meeting the energy and latency constraints. Network-on-chip (NoC) architectures is able to accommodate a large number of IP cores in the same chip implementing a set of complex applications. This leads to different usage of the available buffer space in the routers of the NoC system. In this work we propose power and the systematic design of novel NOC-based architectures, which realize DSP applications. Additionally, we present an integrated node resource management technique that combines priority assignment and buffer sizing so that the NoC system to best serve requirements of the considered Finally, to best of our knowledge, the implementation of DSP applications in 3D NOC architectures took place for first time. DSP applications. The proposed approach has been evaluated both on 2D and 3D mesh topologies by employing an NoC simulator and four real DSP/multimedia applications gaining an average of 34% on energytimesdelay product for each application. Finally, to best of our knowledge, the implementation of DSP applications in 3D NOC architectures took place for first time.