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We report for the first time that extreme EOT scaling and low n/p VTHs can be achieved simultaneously. Underlying mechanisms that enable EOT scaling and EWF tuning are explained and the fundamental device parameters including reliability of the extremely scaled devices are discussed. Record low gate leakage, appropriately low VTHs and competitive carrier mobilities in this work demonstrate the gate stack technology that is consistent with the sub-22 nm node requirements.
VLSI Technology, 2009 Symposium on
Date of Conference: 16-18 June 2009