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Sub-10 nm gate-all-around CMOS nanowire transistors on bulk Si substrate

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8 Author(s)
Ming Li ; Advanced Technology Development Team 1, Semiconductor R&D Center, Samsung Electronics Co. Ltd., San 24, Nongseo-Dong, Kiheung-Ku, Yongin-City, Kyoungi-Do, 449-711, KOREA ; Kyoung Hwan Yeo ; Sung Dae Suk ; Yun Young Yeoh
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In this paper, sub-10 nm gate-all-around (GAA) CMOS silicon nanowire field-effect transistors (SNWFET) on bulk Si substrate are fabricated successfully for the first time with 13-nm-diameter silicon nanowire channel. On-state currents of 1494/1054 muA/mum at off leakage currents of 102/6.44 nA/mum are obtained for N/PMOS, respectively. The impacts of nanowire diameter (DNW) and gate oxide thickness (TOX) as well S/D parasitic resistance (RSD) on performance are investigated in details.

Published in:

2009 Symposium on VLSI Technology

Date of Conference:

16-18 June 2009