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TSV and 3D wafer bonding technologies for advanced stacking system and application at ITRI

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4 Author(s)

Due to the feature of vertically chip-to-chip or chip-to-wafer stacking, the properties and characterization of through-hole vertical interconnects, microbumping, and bonding technologies will be the core competences to achieve a high reliable stacking results. ITRI mainly focuses on the investigation of the quality of low cost interconnect fabrication technology to meet the reliability requirement for 3D chip stacking interconnects. In this paper, we elucidate the interconnect technology for a stacked System in Package (SiP) test vehicle. Compared to the vertical interconnects developed recently, we provide a lower cost solution for both of TSV and microbumping. Based on the result of void-free TSVs, and reliability test, the low resistance of 20-chips stacking feature can be found and thermal dissipation and thermal-mechanical study during this work are discussed. The chip thickness used here is less than 100 mum and ITRI's test vehicles showed the outstanding interconnect reliability during bending and thermal cycling test. We demonstrated that the newly low cost 3D interconnects results are potentially candidate for 3D stacking systems.

Published in:

VLSI Technology, 2009 Symposium on

Date of Conference:

16-18 June 2009