By Topic

Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

18 Author(s)

This paper presents for the first time the successful integration of laser-only annealing in a high-k / metal gate first process flow with functional ring oscillators. The process has been optimized to limit defect creation, reduce poly-silicon resistance and obtain good capping/high-k intermixing. EOT reduction with less eWF roll-off, excellent device scalability without performance penalty and Vth-matching improvement compared to spike have been achieved.

Published in:

VLSI Technology, 2009 Symposium on

Date of Conference:

16-18 June 2009