Optimized ultra-low thermal budget process flow for advanced High-K / Metal gate first CMOS using laser-annealing technology

This paper presents for the first time the successful integration of laser-only annealing in a high-k / metal gate first process flow with functional ring oscillators. The process has been optimized to limit defect creation, reduce poly-silicon resistance and obtain good capping/high-k intermixing. EOT reduction with less eWF roll-off, excellent device scalability without performance penalty and Vth-matching improvement compared to spike have been achieved.