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NiO resistance change memory with a novel structure for 3D integration and improved confinement of conduction path

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2 Author(s)
Byoungil Lee ; Center for Integrated Systems and Dept. of Electrical Engineering, Stanford University, CA 94305, U.S.A. ; H. -S. Philip Wong

We demonstrated a novel 3D integration compatible structure for NiO nonvolatile memory. In this new structure, the programming area does not involve the surface of the NiO film, thus, device characteristics would be more consistent. Its scalability has been proven down to a 48nm X 48nm cell size. The focused E-field in this structure improves the confinement of the conduction path and results in better uniformity in the LRS of the NiO memory cells. Furthermore, this new structure showed a lower RESET current (~90 muA) and better ON/OFF margin than the conventional structure.

Published in:

2009 Symposium on VLSI Technology

Date of Conference:

16-18 June 2009