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Processing while routing: a network-on-chipbased parallel system

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4 Author(s)
Fernandes, S.R. ; Dept. of Exact Sci. & Natural, Rural Fed. Univ. of the Semi-Arid, Mossoro, Brazil ; Oliveira, B.C. ; Costa, M. ; Silva, I.S.

Technology integration has increased to the point where the development of multi-core processor architectures is a market reality nowadays. In this scenario, the interconnection network has a critical function when the number of cores increases, since it is impossible to use bus-based solutions. Other interconnection solutions have been employed. However, they are area and power expensive. This paper approaches this problem with a new NoC-based architecture and a new computation mode. It proposes the utilisation of network-on-chip not only as interconnection but also as the processing datapath.

Published in:

Computers & Digital Techniques, IET  (Volume:3 ,  Issue: 5 )