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A Compact High-Efficiency CMOS Power Amplifier With Built-in Linearizer

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2 Author(s)
Chien-Chang Huang ; Dept. of Commun. Eng., Yuan Ze Univ., Taoyuan, Taiwan ; Wu-Chieh Lin

In this letter, a compact high-efficiency CMOS power amplifier (PA) with built-in linearizer that works at 2.4 GHz using TSMC 0.18 mum technology for digital wireless communications applications is presented. The cascode configuration is utilized to overcome the low break-down voltage problem and the hot-carrier effects for high power operations of CMOS devices. The linearizer design reduces the AM-AM quantities to extend the P1 dB point while the AM-PM distortions are improved as well. The final designed PA exhibits P1 dB of 20.6 dBm and 24.6% power-added-efficiency (PAE) with 35 dBm output-intercept-point in the third order (OIP3). The saturated output power is 22 dBm with 30% in PAE, while the chip size is less than 1 mm2.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:19 ,  Issue: 9 )

Date of Publication:

Sept. 2009

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