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X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing

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4 Author(s)
Jia Li ; Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China ; Qiang Xu ; Yu Hu ; Xiaowei Li

Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both shift and capture phases, which can cause circuits' reliability concerns during manufacturing test. This paper proposes a novel X-filling technique, namely “iFill”, to address the above issue, by analyzing the impact of X-bits on switching activities of the circuit nodes in the two different phases. In addition, different from prior X -filling methods for shift-power reduction that can only reduce shift-in power, our method is able to cut down power consumptions in both shift-in and shift-out processes. Experimental results on benchmark circuits show that the proposed technique can guarantee the power safety in both shift and capture phases during at-speed scan-based testing.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 7 )