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An Area-Efficient LDPC Decoder Architecture and Implementation for CMMB Systems

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3 Author(s)
Kai Zhang ; Dept. of Electr. & Comput. Eng., Worcester Polytech. Inst., Worcester, MA, USA ; Xinming Huang ; Zhongfeng Wang

This paper presents an area-efficient LDPC decoder architecture for the China multimedia mobile broadcasting (CMMB) standard. Several techniques are adopted to reduce memory size, including the min-sum algorithm (MSA), optimal bit-width quantization of the iterative messages and reduced complexity for the interconnect network. The decoder for the rate-1/2 9216-bit code is implemented using the 90 nm 1.0 V CMOS technology. It achieves the decoding throughput of 48 Mbps at 5 iterations when operating at 60 MHz and the power dissipation is only 34 mW.

Published in:

2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors

Date of Conference:

7-9 July 2009