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An Input Triggered Polymorphic ASIC for H.264 Decoding

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9 Author(s)
Rao, A. ; Indian Inst. of Sci., Bangalore, India ; Alle, M. ; V, S. ; Shaik, R.
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This paper reports the design of an input-triggered polymorphic ASIC for H.264 baseline decoder. Hardware polymorphism is achieved by selectively reusing hardware resources at system and module level. Complete design is done using ESL design tools following a methodology that maintains consistency in testing and verification throughout the design flow. The proposed design can support frame sizes from QCIF to 1080p.

Published in:

Application-specific Systems, Architectures and Processors, 2009. ASAP 2009. 20th IEEE International Conference on

Date of Conference:

7-9 July 2009

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