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Parallel Prefix Ling Structures for Modulo 2^n-1 Addition

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2 Author(s)
Jun Chen ; Dept. of Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK, USA ; Stine, J.E.

Parallel-prefix adders draw significant amounts of attention within general-purpose and application-specific architectures because of their logarithmic delay and efficient implementation in VLSI. This paper proposes a scheme to enhance parallel-prefix adders for modulo 2n - 1 addition by incorporating Ling equations into parallel-prefix structures. As opposed to previous research, this work clarifies the use of Ling equations for Modulo and provides enhancements to its implementation. Results are given in this work for a placed and routed design within a variation-aware 45 nm technology. The implementation results show a significant improvement in delay and even a reduction in power dissipation.

Published in:

Application-specific Systems, Architectures and Processors, 2009. ASAP 2009. 20th IEEE International Conference on

Date of Conference:

7-9 July 2009

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