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A Parallel Memory System Model for Multi-core Processor

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4 Author(s)
Mengxiao Liu ; Sch. of Comput. Sci. & Technol., Beijing Inst. of Technol., Beijing, China ; Weixing Ji ; Xing Pu ; Jiaxin Li

Modern multi-core processors are predominant in improving performance of parallel applications. This paper discusses a triple-based multi-core architecture which provides native support for object-oriented methodology and applications in hardware level. The model explicitly represents objects and supports messaging-based communication, which maps well to the standard style of interaction in object oriented languages. However, the Memory Wall is still the bottleneck which should be resolved to decrease the disparity between how fast a CPU can operate on data and how fast it can get data. A hierarchy shared memory system (HSM) working with the partially-inclusive cache mapping policy is proposed. And a new object management model is presented, which use object table and recycle stack scheme to supports explicit dynamic object management. Our cache design presents an innovative solution to handling the costs of cache coherence by allowing applications to control the amount of sharing between cores. Experimental analysis based on comparisons between our objects management and other common link structured object organization methods shows that our method is predominant in spatial and temporal aspects on memory parallel access efficiency and costs less storage space to organize objects.

Published in:

Networking, Architecture, and Storage, 2009. NAS 2009. IEEE International Conference on

Date of Conference:

9-11 July 2009