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As technology scales, designing a massively parallel multi-cores system atop less reliable hardware architecture poses great challenges for researchers and designers. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. We present a variation-aware multi-level scheduling and power management methodology for application-specific multiprocessor system-on-chip (MPSoC) to mitigate the impact of process variations and to optimize the power consumption. The methodology combines both static and dynamic scheduling and tackles the scheduling problem at several abstraction levels according the granularity of the application tasks, processing nodes and the on-chip communication network. The first levels of scheduling allow the local optimization, design space exploration and take into account the variations parameters. The last level, is based run-time scheduling, allows dynamic power management and global on-line optimization.
Date of Conference: 24-26 June 2009