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A new SRAM cell model, SRAMT, is presented providing a scalable solution to soft error for various energy levels of protection with minimal power consumption and write time penalties. Our model is based on a classic 6 transistor inner core SRAM cell and an outer core consisting of enhanced tri-state inverters. The outer core will absorb a particle strike at a sensitive node of the SRAM cell without a major impact on write time performance or area overhead. The model provides an on-demand protection due to the fact that the outer core can be shut off during non-essential operating mode. The on-demand aspect of the design provides a much more favorable power consumption overhead compared to the existing hardening technique. The gains in power consumption overhead reduction increase as we scale down the process technology from 90 nm to 32 nm. We simulated extensively our model and provided results for various energy levels of soft error protection. We also compared our method to the standard hardening technique in terms of layout area, performance and power consumption overhead for for 90 nm, 65 nm, 45 nm and 32 nm process technologies.