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Effect of bias stress on mechanically strained low temperature polycrystalline silicon thin film transistor on stainless steel substrate

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3 Author(s)
Peng, I-Hsuan ; Department of Materials Science and Engineering, National Tsing-Hua University, 101, Section 2, Kuang-Fu Road, Hsinchu, Taiwan 30013, Republic of China ; Liu, Po-Tsun ; Wu, Tai-Bor

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This paper reported the variation in performance of bias stressed low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) fabricated on metal foil substrate for flexible display applications. The mobility, threshold voltage (Vth), and trap density (Nt) of the proposed p-channel poly-Si TFT as a function of curvature radii were investigated. The significant increase in Vth by 9% was observed as the compressive or tensile mechanical strain increases to 0.1%. In addition, the hole mobility increases by 7% due to an increased compressive strain of 0.1%, while hole mobility decreases by 3.5% with the increase in tensile strain of 0.1%. After dc bias stressing, the LTPS TFT with mechanical strain had better performance than that on flat state in both the mobility drop and Vth shift. Mechanical strain influences the lattice arrangement and electric field at the drain electrode region that resisted device degradation in early stressing period.

Published in:

Applied Physics Letters  (Volume:95 ,  Issue: 4 )