By Topic

An implementation of fully analogue sum-of-product neural models in VLSI

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Daniell, PM. ; Kent Univ., Canterbury, UK ; Waller, W.A.J. ; Bisset, D.L.

Neural networks that use digital or partly digital processing units have a restricted set of applications, and also are constrained by the set of learning rules that can be used with them. Analogue networks have a greater flexibility in their learning algorithms and a larger domain of problems which they can solve. The flexibility of an analogue output capability can also be used to give an idea of the certainty or accuracy of results. The design was fabricated using a 2 μm CMOS fabrication process. This provides a relatively low cost, easily available medium for research and would allow easy fabrication of any products arriving from this research on industrial processes. The implementation uses pulse frequency modulation to achieve analogue input and output capability, and uses a pulse width modulation method to realise the synaptic multiplication component. This pulse coding technique reduces the size and complexity of the synaptic multiplier which has to be repeated for each neural connection in the network. This greatly reduces the silicon area required for the architecture

Published in:

Artificial Neural Networks, 1989., First IEE International Conference on (Conf. Publ. No. 313)

Date of Conference:

16-18 Oct 1989