Test generation and logic/fault simulation of programmable logic arrays: optimized partitioning techniques for parallel processing

Much research has been done to increase the efficiency for PLA test generation algorithms. However, the overall gains achieved with the increased efficiency do not keep pace with the increase in PLA size, e.g. computation times are still excessive. For large PLAs the time needed to generate test vectors and to verify correctness of actual implementation on uniprocessor systems is quite prohibitive. However, the recent availability of multiprocessors makes possible great improvements in potential performance for test generation as well as logic/fault simulation. Research using multiprocessors for PLA testing and simulation is still in the very early stages of development.