Notification:
We are currently experiencing intermittent issues impacting performance. We apologize for the inconvenience.
By Topic

VLSI design and implementation of a discrete cosine transform chip for video compression using high level synthesis tools

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Subramani, N. ; BusLogic Inc., Santa Clara, CA, USA ; Ogunfunmi, T.

A new implementation for computing a Discrete Cosine Transform (DCT) is presented. A DCT chip is designed using a Hardware Description Language viz. Verilog. The DCT chip designed is based on algorithms which can be implemented using Distributed Arithmetic. The results of these parallel processes are then combined to obtain the DCT. This implementation enables evaluation of the algorithm in a functional or behavioral form. The netlist of the DCT chip is obtained using Cadence Synthesis tools

Published in:

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on  (Volume:1 )

Date of Conference:

3-5 Aug 1994