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High-level synthesis of fast video compression algorithms

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2 Author(s)
Deb, A. ; DesignWare Group, Synopsys Inc., Mountain View, CA, USA ; Nam Ling

The performance targets for real time Multimedia needs make it necessary that core portions of video compression algorithms be constructed in hardware. The mapping of such algorithms into hardware has been an arduous task so far due to the differing design paradigms. Algorithms are designed to reduce software complexity measures, whereas hardware design involves reducing control complexity and hardware resources, and trading off one for the other. Usually, requiring a bottom up approach. With the advent of behavioral synthesis tools such algorithms can be written in a hardware description language, such as VHDL, preserving its high level content as well as allowing to explore various hardware architectures in a rapid manner. We show some representative algorithms of video compression and investigate various architectures that can be synthesized using Synopsys' Behavioral Compiler. We find that certain descriptions of the algorithm make them well suited for hardware mapping. The conclusion is that there exist a hardware form for each of the algorithms that preserve the semantics of the original algorithm but yet can be quickly and efficiently mapped to hardware

Published in:

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on  (Volume:1 )

Date of Conference:

3-5 Aug 1994