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A design methodology for low power, reduced area, reliable CMOS buffers

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2 Author(s)
Cherkauer, B.S. ; Dept. of Electr. Eng., Rochester Univ., NY, USA ; Friedman, E.G.

Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of primary concern in tapered buffer design. Each places a separate, often conflicting constraint on the design of a tapered buffer. This paper presents a unified design methodology for CMOS tapered buffers which permits trade-offs to be easily made among these four performance criteria. The methodology utilizes analytical expressions for each of the performance criteria. A process dependent look-up table is constructed based on these expressions and is used in conjunction with application-specific performance constraints to efficiently determine the optimal implementation for each particular buffer instantiation

Published in:

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on  (Volume:1 )

Date of Conference:

3-5 Aug 1994