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Post-silicon timing yield enhancement using dual-mode elements

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3 Author(s)
Kim, W. ; Div. of Electr. & Comput. Eng., POSTECH, Pohang, South Korea ; Park, H.S. ; Kim, Y.H.

A simple but effective technique for timing yield enhancement is presented. The proposed technique tunes circuit timing using dual-mode elements, which are special logic gates that can change delay-leakage characteristics at the post-silicon level. In experiments using the ISCAS-85 benchmarks, the proposed technique reduced the timing failure rate by 59.52% on average.

Published in:

Electronics Letters  (Volume:45 ,  Issue: 16 )