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Low-jitter design method based on Wn-domain jitter analysis for 10 Gbit/s clock and data recovery ICs

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6 Author(s)
Kishine, K. ; Univ. of Shiga Prefecture, Hikone, Japan ; Inaba, H. ; Nakamura, M. ; Nakamura, M.
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A low-jitter design method based on omegan-domain jitter analysis for the clock and data recovery (CDR) ICs using the linear phase-locked loop (PLL) is proposed. Using this method, the loop parameters of the PLL can be optimised, which makes it possible to design the CDR IC for various targets.

Published in:

Electronics Letters  (Volume:45 ,  Issue: 16 )

Date of Publication:

July 30 2009

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