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In this study, a novel idea is proposed to test arithmetic circuits with both acceptable number of test patterns (NTP) and hardware overhead (HO). First, highly scalable full adder and full substractor are proposed. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between the NTP and the HO, which is a function of n. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. An iterative logic array (ILA) based on these scalable cells will still be C-testable. Based on the novel bijective and scalable cells, the authors propose C-testable designs for multiplier-accumulator (MAC), N-tap finite impulse response (FIR) filter and matrix multiplication, where the (HO, NTP) pairs with n = 2 are only about (4.87%, 74). For 4 times 4 matrix multiplication, the total test time of the proposed method is only about 0.19% of that with the scan-chain method. With scalable and bijective cells, all the proposed ILA solutions can be connected together into a bigger non-homogeneous ILA and save lots of test pins and build-in self-test (BIST) area. In addition, the proposed scalable cells induce a simple and systematic way to have balanced results. The proposed technique makes the ILA-based DFT schemes more practical, systematic and useful for real-world complex applications.