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Performance Modeling of Low- k /Cu Interconnects for 32-nm-Node and Beyond

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3 Author(s)
Tada, M. ; Device Platforms Res. Labs., NEC Corp., Sagamihara, Japan ; Inoue, N. ; Hayashi, Y.

Challenges and issues with the scaling of low-k/Cu interconnects in ultra-large-scale integration (ULSI) devices are reviewed, and the performance of interconnects is featured by considering the effect of the resistance and capacitance per unit interconnect length or the minimum grid length. The grid-scaled resistance-capacitance (GSRC) model is proposed to compare the interconnect performance at various technology nodes. Introduction of low-k films to reduce the line capacitance improves the per-grid value of the resistance-capacitance product, however, the abrupt increment of the line resistivity due to the small-size effect consumes the benefit of the capacitance beyond 32-nm-node. We also discuss power consumption in interconnects with different low-k structures based on experimental works. Continuous reduction of effective k-value (K eff) is needed to reduce the active power consumption. The way to reduce the interconnect resistance while keeping the interconnect reliability high is a key challenge, particularly for deeply scaled-down ULSIs.

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Electron Devices, IEEE Transactions on  (Volume:56 ,  Issue: 9 )