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Low Dynamic Power High Performance Adder

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3 Author(s)
Senejani, M.N. ; Dept. of Comput. Eng., Islamic Azad Univ. Ashtian Branch, Ashtian, Iran ; Hosseinghadiry, M. ; Miryahyaei, M.

This paper presents the design of high performance low dynamic power circuits using a new CMOS dynamic logic family, and analyzes power and performance of them, and compares the proposed logic to standard CMOS dynamic logic. Results show that the dynamic power reduces at least 26% and the performance improves at least 4.6 times for a 32 bits ripple carry adder in comparison to standard domino logic. In other hand charge redistribution, limitation of non-inverting only logic and need for output inverter problems of domino logic are completely eliminated.

Published in:

Future Computer and Communication, 2009. ICFCC 2009. International Conference on

Date of Conference:

3-5 April 2009