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Opportunities for parallelism when implementing algorithms in VHDL — a case study — Shift-Or

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3 Author(s)
Barry Schulz ; School of Engineering, Grand Valley State University, Grand Rapids, Michigan 49504, USA ; Chirag Parikh ; Christian Trefftz

Field Programmable Gate Arrays (FPGAs) are becoming pervasive in High Performance Computing systems, making it possible for developers to implement algorithms (or at least portions of algorithms) directly in hardware using Hardware Description Languages. The Shift-Or algorithm for exact string matching was implemented using VHDL on a XILINX FPGA. This paper discusses some of the opportunities for performance improvement offered by VHDL that were used when implementing the Shift-Or algorithm.

Published in:

2009 IEEE International Conference on Electro/Information Technology

Date of Conference:

7-9 June 2009