Referenced Items are not available for this document.
Inserting redundancy to arithmetic codes is a common strategy to add error detection capability to this well-known family of source codes. By using this strategy error correction is possible through some decoding algorithms such as Viterbi decoder. In this paper a system has proposed that uses finite state integer arithmetic codes (FSAC) as a joint source-channel code in combination with a cyclic redundancy check (CRC) and a List Viterbi decoder. The proposed scheme has shown better performance than previous ones.
Published in:
Electro/Information Technology, 2009. eit '09. IEEE International Conference on
Date of Conference: 7-9 June 2009
- Page(s):
- 19 - 22
- E-ISBN :
- 978-1-4244-3355-1
- Print ISBN:
- 978-1-4244-3354-4
- INSPEC Accession Number:
- 10804172
- Conference Location :
- Windsor, ON
- Digital Object Identifier :
- 10.1109/EIT.2009.5189577
- Product Type:
- Conference Publications
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