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Inserting redundancy to arithmetic codes is a common strategy to add error detection capability to this well-known family of source codes. By using this strategy error correction is possible through some decoding algorithms such as Viterbi decoder. In this paper a system has proposed that uses finite state integer arithmetic codes (FSAC) as a joint source-channel code in combination with a cyclic redundancy check (CRC) and a List Viterbi decoder. The proposed scheme has shown better performance than previous ones.