Skip to Main Content
Functional verification plays an important role in the design flow of an intellectual property (IP) core and, in general, of an embedded system. The industrial trend of the last two decades has been to produce more and more complex embedded systems by integrating several IP cores on a single chip die; while this is easily possible thanks to the availability of ready-to-use off-the-shelf components, the functional verification of the whole system becomes a major concern. Hand-written HDL test-benches or formal approaches to verification are no more feasible methods to assess good quality verification in a reasonable amount of time. To meet the new requirements of complex systems design, EDA companies are developing verification tools that bring rapid development, reusability concepts and automation techniques also in the world of functional verification. This work faces the issue of providing an automated verification environment for a network-on-chip component that is part of a complex communication infrastructure within a multi-core embedded system. In this context, reusability is a key feature of the environment, because it allows the user to easily move from component verification to network verification. The verification tool used in this work is Spec-man elite by Cadence and the IP it is applied to is a spidergon-STNoC (by STMicroelectronics) component. Verification environment design guidelines are provided together with a final coverage report summary.