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Soft Error Rate Analysis for Combinational Logic Using an Accurate Electrical Masking Model

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2 Author(s)
Feng Wang ; Qualcomm Inc., San Diego, CA, USA ; Yuan Xie

Accurate electrical masking modeling represents a significant challenge in soft error rate analysis for combinational logic circuits. In this paper, we use table lookup MOSFET models to accurately capture the nonlinear properties of submicron MOS transistors. Based on these models, we propose and validate the transient pulse generation model and propagation model for soft error rate analysis. The pulse generated by our pulse generation model matches well with that of HSPICE simulation, and the pulse propagation model provides nearly one order of magnitude improvement in accuracy over the previous models. Using these two models, we propose an accurate and efficient block-based soft error rate analysis method for combinational logic circuits.

Published in:

Dependable and Secure Computing, IEEE Transactions on  (Volume:8 ,  Issue: 1 )

Date of Publication:

Jan.-Feb. 2011

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